Non-scan design-for-testability of RT-level data paths
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Automatic test pattern generation for functional RTL circuits using assignment decision diagrams
Proceedings of the 37th Annual Design Automation Conference
VHDL: Analysis and Modeling of Digital Systems
VHDL: Analysis and Modeling of Digital Systems
RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems
Journal of Electronic Testing: Theory and Applications
Synthesis of Scan Chains for Netlist Descriptions at RT-Level
Journal of Electronic Testing: Theory and Applications
Inserting Scan at the Behavioral Level
IEEE Design & Test
RT-Level ITC'99 Benchmarks and First ATPG Results
IEEE Design & Test
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Orthogonal Scan: Low-Overhead Scan for Data Paths
Proceedings of the IEEE International Test Conference on Test and Design Validity
Improving Gate Level Fault Coverage by RTL Fault Grading
Proceedings of the IEEE International Test Conference on Test and Design Validity
High-coverage ATPG for datapath circuits with unimplemented blocks
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Fast test generation for circuits with RTL and gate-level views
Proceedings of the IEEE International Test Conference 2001
Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
REGISTER-TRANSFER LEVEL FAULT MODELING AND TEST EVALUATION TECHNIQUES FOR VLSI CIRCUITS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Comparing Functional and Structural Tests
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Evaluating ATE Features in Terms of Test Escape Rates and Other Cost of Test Culprits
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Good Scan = Good Quality Level? Well, It Depends "
ITC '02 Proceedings of the 2002 IEEE International Test Conference
High-level and hierarchical test sequence generation
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Timing-based delay test for screening small delay defects
Proceedings of the 43rd annual Design Automation Conference
Spectral RTL Test Generation for Gate-Level Stuck-at Faults
ATS '06 Proceedings of the 15th Asian Test Symposium
Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects
ATS '06 Proceedings of the 15th Asian Test Symposium
Functional Test Selection for High Volume Manufacturing
MTV '06 Proceedings of the Seventh International Workshop on Microprocessor Test and Verification
Efficient RTL Coverage Metric for Functional Test Selection
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Fault-dependent/independent Test Generation Methods for State Observable FSMs
ATS '07 Proceedings of the 16th Asian Test Symposium
ATS '08 Proceedings of the 2008 17th Asian Test Symposium
Coverage-directed test generation through automatic constraint extraction
HLDVT '07 Proceedings of the 2007 IEEE International High Level Design Validation and Test Workshop
Model-driven test generation for system level validation
HLDVT '07 Proceedings of the 2007 IEEE International High Level Design Validation and Test Workshop
RT-Level Deviation-Based Grading of Functional Test Sequences
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Automatic Selection of Internal Observation Signals for Design Verification
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Deviation-based LFSR reseeding for test-data compression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Functional test sequences are often used in manufacturing testing to target defects that are not detected by structural test. However, they suffer from low defect coverage since they are mostly derived in practice from existing design-verification test sequences. Therefore, there is a need to increase their effectiveness using design-for-testability (DFT) techniques. We present a DFT method that uses the register-transfer level (RTL) output deviations metric to select observation points for an RTL design and a given functional test sequence. Simulation results for six ITC驴99 circuits show that the proposed method outperforms two baseline methods for several gate-level coverage metrics, including stuck-at, transition, bridging, and gate-equivalent fault coverage. Moreover, by inserting a small subset of all possible observation points using the proposed method, significant fault coverage increase is obtained for all benchmark circuits.