Design validation of multithreaded architectures using concurrent threads evolution
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences
Journal of Electronic Testing: Theory and Applications
Automatic assertion extraction via sequential data mining of simulation traces
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Online selection of effective functional test programs based on novelty detection
Proceedings of the International Conference on Computer-Aided Design
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Generating tests to achieve high coverage in simulation-based functional verification can be very challenging. Constrained-random and coverage-directed test generation methods have been proposed and shown with various degrees of success. In this paper, we propose a new tool built on top of an existing constrained random test generation framework. The goal of this tool is to extract constraints from simulation data for improving controllability of internal signals. We present two automatic constraint extraction algorithms. Extracted constraints can be put back into constrained test-bench to generate tests for simultaneously controlling multiple signals. We demonstrate the effectiveness and scalability of the constraint extraction tool based on experiments on OpenSparc T1 microprocessor.