Behavioral fault simulation in VHDL
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
On behavior fault modeling for digital designs
Journal of Electronic Testing: Theory and Applications
Testability analysis and improvement from VHDL behavioral specifications
EURO-DAC '94 Proceedings of the conference on European design automation
Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A heuristic chip-level test generation algorithm
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Principles of verifiable RTL design: a functional coding style supporting verification processes in Verilog
Test Sets and Reject Rates: All Fault Coverages are Not Created Equal
IEEE Design & Test
From Hardware to Software Testability
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Test Synthesis in the Behavioral Domain
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
From Specification Validation to Hardware Testing: A Unified Method
Proceedings of the IEEE International Test Conference on Test and Design Validity
Implicit test generation for behavioral VHDL models
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Behavioral Fault Modeling in a VHDL Synthesis Environment
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
On the decline of testing efficiency as fault coverage approaches 100%
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Testability metrics for synthesis of self-testable designs and effective test plans
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Defect level evaluation in an IC design environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage
Journal of Electronic Testing: Theory and Applications
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level
Journal of Electronic Testing: Theory and Applications
RTL Test Pattern Generation for High Quality Loosely Deterministic BIST
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
Functional test has long been viewed as unfitted for high-quality production test. The purpose of this paper is to propose a RTL-based test generation methodology which can rewardingly be used both for design validation and to enhance the test effectiveness of classic, gate-level test generation. The proposed methodology leads to high Defects Coverage (DC) and to relatively short test sequences, thus allowing low-energy operation in test mode. The test effectiveness, regarding DC, is shown to be weakly dependent on the structural implementation of the behavioral description. The usefulness of the methodology is ascertained using the VeriDOS simulation environment and the CMUDSP and Torch ITC'99 benchmark circuits.