Test Data Decompression for Multiple Scan Designs with Boundary Scan
IEEE Transactions on Computers
RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems
Journal of Electronic Testing: Theory and Applications
Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level
Proceedings of the IEEE International Test Conference 2001
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Defect level evaluation in an IC design environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Probabilistic Method for the Computation of Testability of RTL Constructs
Proceedings of the conference on Design, automation and test in Europe - Volume 1
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
High quality Built-In Self Test (BIST) needs to efficiently tackle the coverage of random-pattern-resistant (r.p.r) defects. Several techniques have been proposed to cover r.p.r faults at logic level, namely, weighted pseudo-random and mixed-mode. In mixed-mode test pattern generation (TPG) techniques, deterministic tests are added to pseudo-random vectors to detect r.p.r faults. Recently, a RTL mixed-mode TPG technique has been proposed to cover r.p.r defects, the mask-based BIST technique. The purpose of this paper is to present mask-based BIST TPG improvements, namely in two areas: RTL estimation of the test length to be used for each mask, in order to reach high Defects Coverage (DC), and the identification of an optimum mask for each set of nested RTL conditions. Results are used to predict the number of customized vectors for each mask of one ITC'99 benchmark module.