Altering a Pseudo-Random Bit Sequence for Scan-Based BIST

A Test Methodology for High Performance MCMs

Journal of Electronic Testing: Theory and Applications - Special issue on multi-chip testing and design for testability

Deterministic BIST with Multiple Scan Chains

Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop

Deterministic BIST with Partial Scan

Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999

Minimized Power Consumption for Scan-Based BIST

Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999

Circuit partitioning for efficient logic BIST synthesis

Proceedings of the conference on Design, automation and test in Europe

A testability metric for path delay faults and its application

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference

2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test

GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI

Embedded test control schemes for compression in SOCs

Proceedings of the 39th annual Design Automation Conference

A mixed-mode BIST scheme based on folding compression

Journal of Computer Science and Technology

A Unified DFT Approach for BIST and External Test

Journal of Electronic Testing: Theory and Applications

A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters

Journal of Electronic Testing: Theory and Applications

Application of Deterministic Logic BIST on Industrial Circuits

Journal of Electronic Testing: Theory and Applications

Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST

Journal of Electronic Testing: Theory and Applications

Deterministic BIST with multiple scan chains

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Accumulator based deterministic BIST

ITC '98 Proceedings of the 1998 IEEE International Test Conference

A Ring Architecture Strategy for BIST Test Pattern Generation

Journal of Electronic Testing: Theory and Applications

Modeling Fault Coverage of Random Test Patterns

Journal of Electronic Testing: Theory and Applications

Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

Non-Intrusive BIST for Systems-on-a-Chip

ITC '00 Proceedings of the 2000 IEEE International Test Conference

A MIXED MODE BIST SCHEME BASED ON RESEEDING OF FOLDING COUNTERS

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Test Structure Verification of Logical BIST: Problems and Solutions

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Application of Deterministic Logic BIST on Industrial Circuits

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Low Power BIST Design by Hypergraph Partitioning: Methodology and Architectures

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Using a Hierarchical DfT Methodology in High Frequency Processor Designs for Improved Delay Fault Testability

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Low Hardware Overhead Scan Based 3-Weight Weighted Random BIST

ITC '01 Proceedings of the 2001 IEEE International Test Conference

TWO-DIMENSIONAL TEST DATA COMPRESSION FOR SCAN-BASED DETERMINISTIC BIST

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Scan Encoded Test Pattern Generation for BIST

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Using BIST Control for Pattern Generation

ITC '97 Proceedings of the 1997 IEEE International Test Conference

On Using Machine Learning for Logic BIST

ITC '97 Proceedings of the 1997 IEEE International Test Conference

An Automatic Validation Methodology for Logic BIST in High Performance VLSI Design

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

Testing strategies for networks on chip

Networks on chip

Minimized Power Consumption For Scan-Based Bist

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes

IEEE Transactions on Computers

Test data compression using dictionaries with selective entries and fixed-length indices

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units

IEEE Transactions on Computers

Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression

Proceedings of the conference on Design, automation and test in Europe - Volume 2

Logic BIST Using Constrained Scan Cells

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium

Scan-BIST based on transition probabilities

Proceedings of the 41st annual Design Automation Conference

RTL Test Pattern Generation for High Quality Loosely Deterministic BIST

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

A seed selection procedure for LFSR-based random pattern generators

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

X-masking during logic BIST and its impact on defect coverage

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Efficient scan-based BIST scheme for low power testing of VLSI chips

Proceedings of the 2006 international symposium on Low power electronics and design

Scan-BIST based on cluster analysis and the encoding of repeating sequences

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Synthesis of irregular combinational functions with large don't care sets

Proceedings of the 17th ACM Great Lakes symposium on VLSI

A BIST TPG for low power dissipation and high fault coverage

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Antirandom testing: a distance-based approach

VLSI Design

CASP: concurrent autonomous chip self-test using stored test patterns

Proceedings of the conference on Design, automation and test in Europe

Study on Expansion of Convolutional Compactors over Galois Field

IEICE - Transactions on Information and Systems

Study on Test Data Reduction Combining Illinois Scan and Bit Flipping

IEICE - Transactions on Information and Systems

Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate

IEICE - Transactions on Information and Systems

Design and verification of the IBM system z10 I/O subsystem chips

IBM Journal of Research and Development

Reducing the storage requirements of a test sequence by using a background vector

Proceedings of the Conference on Design, Automation and Test in Europe

BISD: scan-based built-in self-diagnosis

Proceedings of the Conference on Design, Automation and Test in Europe

Efficient Concurrent Self-Test with Partially Specified Patterns

Journal of Electronic Testing: Theory and Applications

Test data compression using efficient bitmask and dictionary selection methods

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Nine-coded compression technique for testing embedded cores in socs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Weighted pseudorandom hybrid BIST

IEEE Transactions on Very Large Scale Integration (VLSI) Systems