A method for generating weighted random test pattern
IBM Journal of Research and Development
Correlation-reduced scan-path design to improve delay fault coverage
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Constructive Multi-Phase Test Point Insertion for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
At-Speed Test is not Necessarily an AC Test
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Deterministic BIST with multiple scan chains
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A BIST scheme for the detection of path-delay faults
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Automated synthesis of large phase shifters for built-in self-test
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Application of Deterministic Logic BIST on Industrial Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IEEE Design & Test
Test Point Placement to Simplify Fault Detection
IEEE Transactions on Computers
Custom circuit design as a driver of microprocessor performance
IBM Journal of Research and Development
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In this paper a novel hierarchical DfTmethodology is presented which is targeted to improvethe delay fault testability for external testing and scan-basedBIST. After the partitioning of the design intohigh frequency macros, the analysis for delay faulttestability already starts in parallel with theimplementation at the macro level. A specification isgenerated for each macro that defines the delay faulttesting characteristics at the macro boundaries. Thisspecification is used to analyse and improve the delayfault testability by improving the scan chain ordering atmacro-level before the macros are connected togetherinto the total chip network. The hierarchicalmethodology has been evaluated with the instructionwindow buffer core of an out-of-order processor. It wasshown that for this design practically no extrahardware is required.