Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement

Delay fault models and test generation for random logic sequential circuits

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference

Clock grouping: a low cost DFT methodology for delay testing

DAC '94 Proceedings of the 31st annual Design Automation Conference

Path delay ATPG for standard scan design

EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation

A Scan-BIST Structure to Test Delay Faults in Sequential Circuits

Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop

Delay fault testing of IP-based designs via symbolic path modeling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Path delay fault testing using test points

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Test Sets and Reject Rates: All Fault Coverages are Not Created Equal

IEEE Design & Test

IEEE Std 1149.1: Where Are We? Where From Here?

IEEE Design & Test

Delay test of chip I/Os using LSSD boundary scan

ITC '98 Proceedings of the 1998 IEEE International Test Conference

A BIST scheme for the detection of path-delay faults

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Shared I/O-cell structures: a framework for extending the IEEE 1149.1 boundary-scan standard

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Effects of Multi-cycle Sensitization on Delay Tests

VLSID '03 Proceedings of the 16th International Conference on VLSI Design

Delay Fault Testing of Designs with Embedded IP Cores

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

Comparing Functional and Structural Tests

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Too Much Delay Fault Coverage Is a Bad Thing

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Using a Hierarchical DfT Methodology in High Frequency Processor Designs for Improved Delay Fault Testability

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors

Journal of Electronic Testing: Theory and Applications

Delay Testing of SOI Circuits: Challenges with the History Effect

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Delay Fault Testing of IP-Based Designs Via Symbolic Path Modeling

ITC '99 Proceedings of the 1999 IEEE International Test Conference

On test generation for transition faults with minimized peak power dissipation

Proceedings of the 41st annual Design Automation Conference

Efficient techniques for transition testing

ACM Transactions on Design Automation of Electronic Systems (TODAES)

A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals

ICCD '05 Proceedings of the 2005 International Conference on Computer Design

Detection of multiple transitions in delay fault test of SPARC64 microprocessor

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Software-based self-test methodology for crosstalk faults in processors

HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop

Constraint extraction for pseudo-functional scan-based delay testing

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Functional constraints vs. test compression in scan-based delay testing

Proceedings of the conference on Design, automation and test in Europe: Proceedings

Transition delay fault test pattern generation considering supply voltage noise in a SOC design

Proceedings of the 44th annual Design Automation Conference

Functional Constraints vs. Test Compression in Scan-Based Delay Testing

Journal of Electronic Testing: Theory and Applications

Securing Designs against Scan-Based Side-Channel Attacks

IEEE Transactions on Dependable and Secure Computing

Efficient path delay test generation based on stuck-at test generation using checker circuitry

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Controllability of Static CMOS Circuits for Timing Characterization

Journal of Electronic Testing: Theory and Applications

Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique

Journal of Electronic Testing: Theory and Applications

A new delay test based on delay defect detection within slack intervals (DDSI)

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

On path delay testing in a standard scan environment

ITC'94 Proceedings of the 1994 international conference on Test

Chiba Scan Delay Fault Testing with Short Test Application Time

Journal of Electronic Testing: Theory and Applications

Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Flip-flop selection for partial enhanced scan to reduce transition test data volume

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

An on-chip delay measurement technique using signature registers for small-delay defect detection

IEEE Transactions on Very Large Scale Integration (VLSI) Systems