Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
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High-Frequency, At-Speed Scan Testing
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ETW '03 Proceedings of the 8th IEEE European Test Workshop
Constrained ATPG for Broadside Transition Testing
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Static Verification of Test Vectors for IR Drop Failure
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
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VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Pattern Generation and Estimation for Power Supply Noise Analysis
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
On Generating Pseudo-Functional Delay Fault Tests for Scan Designs
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
A novel framework for faster-than-at-speed delay test considering IR-drop effects
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Test scheduling for core-based systems using mixed-integer linear programming
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Layout-aware, IR-drop tolerant transition fault pattern generation
Proceedings of the conference on Design, automation and test in Europe
Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 International Conference on Computer-Aided Design
On reducing scan shift activity at RTL
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
NIM: a noise index model to estimate delay discrepancies between silicon and simulation
Proceedings of the Conference on Design, Automation and Test in Europe
Improved weight assignment for logic switching activity during at-speed test pattern generation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Emulating and diagnosing IR-drop by using dynamic SDF
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Power-safe application of tdf patterns to flip-chip designs during wafer test
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Integration, the VLSI Journal
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Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise is increasing. The supply noise is much larger during at-speed delay test compared to normal circuit operation since large number of transitions occur within a short time frame. Existing commercial ATPG tools do not consider the excessive supply noise that might occur in the design during test pattern generation. In this paper, we first present a case study of a SOC design and show detailed IR-drop analysis, measurement and its effects on design performance during at-speed test. We then propose a novel method to measure the average power of at-speed test patterns, referred to as switching cycle average power (SCAP). A new practical pattern generation methodology is proposed to generate supply noise tolerant delay test patterns using existing capabilities in commercial ATPG tools. The results demonstrate that the new patterns generated using our technique will minimize the supply noise effects on path delay.