A Novel Transition Fault ATPG That Reduces Yield Loss
IEEE Design & Test
Functional constraints vs. test compression in scan-based delay testing
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Transition delay fault test pattern generation considering supply voltage noise in a SOC design
Proceedings of the 44th annual Design Automation Conference
Functional Constraints vs. Test Compression in Scan-Based Delay Testing
Journal of Electronic Testing: Theory and Applications
Conflict driven scan chain configuration for high transition fault coverage and low test power
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Techniques for SAT-based constrained test pattern generation
Microprocessors & Microsystems
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In this paper, we propose a new concept of testing only functionally testable transition faults in Broadside Transition testing via a novel constrained ATPG. For each functionally untestable transition fault f, a set of illegal (unreachable) states that enable detection of f is first computed. This set of undesirable illegal states is efficiently represented as a Boolean formula. Our constrained ATPG then incorporates this constraint formula to generate Broadside vectors that avoid those undesirable states. In doing so, our method efficiently generates a test set for functionally testable transition faults and minimizes detection of functionally untestable transition faults. Because we want to avoid launching and propagating transitions in the circuit that are not possible in the functional mode, a direct bene.t of our method is the reduction of yield loss due to overtesting of these functionally untestable transitions.