Skewed-Load Transition Test: Part 1, Calculus
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Skewed-Load Transition Test: Part 2, Coverage
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Too much delay fault coverage is a bad thing
Proceedings of the IEEE International Test Conference 2001
On Structural vs. Functional Testing for Delay Faults
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
On Achieving Complete Coverage of Delay Faults in Full Scan Circuits using Locally Available Lines
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Constrained ATPG for Broadside Transition Testing
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Proceedings of the conference on Design, automation and test in Europe - Volume 2
On Low-Capture-Power Test Generation for Scan Testing
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction
IEEE Transactions on Computers
Enhanced Broadside Testing for Improved Transition Fault Coverage
ATS '07 Proceedings of the 16th Asian Test Symposium
UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting
IEEE Design & Test
Test pattern generation and clock disabling for simultaneous test time and power reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A novel test application scheme for high transition fault coverage and low test cost
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
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Two conflict-driven schemes and a new scan architecture based on them are presented to improve fault coverage of transition fault. They make full use of the advantages of broadside, skewed-load and enhanced scan testing, and eliminate the disadvantages of them, such as low coverage, fast global scan enable signal and hardware overhead. Test power is also a challenge for delay testing, so our method tries to reduce the test power at the same time. By the analysis of the functional dependency between test vectors in broadside testing and the shift dependency between vectors in the skewed-load testing, some scan cells are selected to operate in the enhanced scan and skewed-load scan mode, while others operate in traditional broadside mode. In the architecture, scan cells with common successors are divided into one chain. With the efficient conflict driven selection methods and partition of scan cells, fault coverage can be improved greatly and test power can be reduced, without sacrificing the test time and test data. Experimental results show that the fault coverage of the proposed method can reach the level of enhanced scan design.