On Low-Capture-Power Test Generation for Scan Testing

Authors:
Xiaoqing Wen;Yoshiyuki Yamashita;Seiji Kajihara;Laung-Terng Wang;Kewal K. Saluja;Kozo Kinoshita
Affiliations:
Kyushu Institute of Technology;Kyushu Institute of Technology;Kyushu Institute of Technology;SynTest Technologies, Inc.;University of Wisconsin - Madison;Osaka Gakuin University
Venue:
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Year:
2005

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Abstract

Research on low-power scan testing has been focused on the shift mode, with little or no consideration given to the capture mode power. However, high switching activity when capturing a test response can cause excessive IR drop, resulting in significant yield loss. This paper addresses this problem with a novel low-capture-power X-filling method by assigning 0ýs and 1ýs to unspecified (X) bits in a test cube to reduce the switching activity in capture mode. This method can be easily incorporated into any test generation flow, where test cubes are obtained during ATPG or by Xbit identification. Experimental results show the effectiveness of this method in reducing capture power dissipation without any impact on area, timing, and fault coverage.