LPTest: a Flexible Low-Power Test Pattern Generator

Authors:
Meng-Fan Wu;Kai-Shun Hu;Jiun-Lang Huang
Affiliations:
Graduate Institute of Electronics Engineering, Dept. of Electrical Engineering,, National Taiwan University, Taipei, Taiwan 106;Graduate Institute of Electronics Engineering, Dept. of Electrical Engineering,, National Taiwan University, Taipei, Taiwan 106;Graduate Institute of Electronics Engineering, Dept. of Electrical Engineering,, National Taiwan University, Taipei, Taiwan 106
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2009

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Abstract

This paper presents a low power test pattern generator, LPTest, that minimizes the peak power consumption during the shift and capture cycles for scan-based stuck-at and transition fault testing. LPTest incorporates both power-aware ATPG and low-power X-filling techniques to achieve higher power reduction. Its enabling technique is a power estimation method which assesses the lower-bounds of the shift-in, shift-out, and capture powers of a partially specified test pattern. The lower-bound estimation method is utilized in LPTest's ATPG engine, dynamic compaction, and X-filling. LPTest has been validated using ISCAS89 benchmark circuits. When considering all cycles, LPTest achieves better than 22% peak WSA (weighted switching activity) reduction for stuck-at and transition faults compared to a commercial ATPG with high merge ratio and random-fill options. Meanwhile, the average power reduction is better than 43%. When only capture power is of concern, LPTest attains more than 46% WSA reduction for stuck-at and transitions.