Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints
Journal of Electronic Testing: Theory and Applications
Scalable Delay Fault BIST for Use with Low-Cost ATE
Journal of Electronic Testing: Theory and Applications
Simultaneous Reduction of Dynamic and Static Power in Scan Structures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
New test data decompressor for low power applications
Proceedings of the 44th annual Design Automation Conference
Efficient partial scan cell gating for low-power scan-based testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
LPTest: a Flexible Low-Power Test Pattern Generator
Journal of Electronic Testing: Theory and Applications
Low-power scan operation in test compression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power supply noise reduction for at-speed scan testing in linear-decompression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power management using test-pattern ordering for wafer-level test during burn-in
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On reducing scan shift activity at RTL
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Single cycle access structure for logic test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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An automatic test pattern generation (ATPG) technique is proposed that reduces switching activity during testing of sequential circuits that have full scan. The objective is to permit safe and inexpensive testing of low-power circuits and bare dies that would otherwise require expensive heat removal equipment for testing at high speed. The approach works with standard scan designs that are commonly used and typically have significantly lower overhead than enhanced scan designs. The proposed ATPG exploits all possible "don't cares" that occur during scan shifting, test application, and response capture to minimize switching activity in the circuit under test. An ATPG that minimizes the number of state inputs that are assigned specific binary values has been developed. Don't cares at state inputs are assigned binary values that cause the minimum number of transitions during scan shifting and don't cares at primary inputs during scan shifting and capture are used to block gates that may have transitions during scan shifting. The proposed technique has been implemented and the generated tests are compared with those generated by a simple PODEM implementation for full scan versions of ISCAS89 benchmark circuits.