Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints

Authors:
Valentin Mureşan;Xiaojun Wang;Valentina Mureşan;Mircea Vlăduţiu
Affiliations:
School of Electronic Engineering, Dublin City University, Dublin 9, Ireland. muresanv@eeng.dcu.ie;School of Electronic Engineering, Dublin City University, Dublin 9, Ireland;“Politehnica” University of Timişoara, România. vmuresan@cs.utt.ro;“Politehnica” University of Timişoara, România
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2004

Citing 17
Cited 1

Test Schedules for VLSI Circuits Having Built-In Test Hardware

IEEE Transactions on Computers - The MIT Press scientific computation series
REAL: a program for REgister ALlocation

DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Test Scheduling and Control for VLSI Built-in Self-Test

IEEE Transactions on Computers
A scheme for overlaying concurrent testing of VLSI circuits

DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Scheduling tests for VLSI systems under power constraints

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of system-on-a-chip test access architectures under place-and-route and power constraints

Proceedings of the 37th Annual Design Automation Conference
An integrated system-on-chip test framework

Proceedings of the conference on Design, automation and test in Europe
On Concurrent Test of Core-Based SOC Design

Journal of Electronic Testing: Theory and Applications
Power-Constrained Block-Test List Scheduling

RSP '00 Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000)
The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power Constraints

VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Minimized Power Consumption For Scan-Based Bist

ITC '99 Proceedings of the 1999 IEEE International Test Conference
Techniques for minimizing power dissipation in scan and combinational circuits during test application

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power scan testing and test data compression for system-on-a-chip

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DS-LFSR: a BIST TPG for low switching activity

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An automatic test pattern generator for minimizing switching activity during scan testing activity

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power profile manipulation: a new approach for reducing test application time under power constraints

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Scheduling Tests for 3D Stacked Chips under Power Constraints

Journal of Electronic Testing: Theory and Applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

Greedy scheduling algorithms are proposed here to improve the test concurrency under power limits. An extended tree growing technique is used to model the power-constrained test scheduling problem in these algorithms. A constant additive model is employed for power dissipation analysis and estimation. The efficiency of this approach is assessed with test scheduling examples and the experimental results are presented. Known list scheduling approaches are proven to give acceptable power-constrained test scheduling results quickly, but not guaranteed to be optimal.