Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Comparison of Classical Scheduling Approaches in Power-Constrained Block-Test Scheduling
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
Power-Conscious Test Synthesis and Scheduling
IEEE Design & Test
Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints
Journal of Electronic Testing: Theory and Applications
Testability Trade-Offs for BIST Data Paths
Journal of Electronic Testing: Theory and Applications
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The left-edge algorithm is adapted in this paper to deal with the problem of unequal-length block-test scheduling under power dissipation constraints. An extended tree growing technique is used in combination with the left-edge algorithm in order to improve the test concurrency under power dissipation limits. Test scheduling example is discussed highlighting further research directions towards an efficient system-level test-scheduling algorithm.