Test Scheduling and Control for VLSI Built-in Self-Test
IEEE Transactions on Computers
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scheduling tests for VLSI systems under power constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ATPG for heat dissipation minimization during scan testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
ATPG for Heat Dissipation Minimization During Test Application
IEEE Transactions on Computers
Power management in high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of system-on-a-chip test access architectures under place-and-route and power constraints
Proceedings of the 37th Annual Design Automation Conference
A survey of design techniques for system-level dynamic power management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Low Power BIST by Filtering Non-Detecting Vectors
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Minimized Power Consumption for Scan-Based BIST
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Testability trade-offs for BIST RTL data paths: the case for three dimensional design space
Proceedings of the conference on Design, automation and test in Europe
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Optimal Vector Selection for Low Power BIST
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems
ATS '99 Proceedings of the 8th Asian Test Symposium
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Low Power Testing of VLSI Circuits: Problems and Solutions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BIST hardware synthesis for RTL data paths based on test compatibility classes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Power dissipation during test application is an emergingproblem due to yield and reliability concerns. This paperfocuses on BIST for RTL data paths and discusses testabilitytrade-offs in terms of test application time, BIST areaoverhead and power dissipation. Using a complex validationflow and experimental data for over 30,000 testabledata paths, it is shown how test application time decreasesasymptotically when increasing power constraints. Further,it is experimentally demonstrated why power conscious testsynthesis and test scheduling algorithms are required due tolarge variations in useless power dissipation as test applicationtime decreases. Finally, while previous research hasoutlined that test application time decreases as BIST areaoverhead increases, this paper shows that in order to reachhigh quality solutions in terms of test application time andBIST area overhead under given power constraints, a threedimensional design space needs to be explored.