Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
IDDQ Test: Sensitivity Analysis of Scaling
Proceedings of the IEEE International Test Conference on Test and Design Validity
So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment
Proceedings of the IEEE International Test Conference
Towards a Standard for Embedded Core Test: An Example
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits
IEEE Transactions on Computers
Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits
Journal of Electronic Testing: Theory and Applications
The Mutating Metric for Benchmarking Test
IEEE Design & Test
Testing in a Noisy Environment
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Design for Testability in Nanometer Technologies; Searching for Quality
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Testability Trade-Offs for BIST Data Paths
Journal of Electronic Testing: Theory and Applications
| Hi-index | 4.10 |
Test engineers are already hard pressed to ensure the quality of ICs despite ever shorter time to market and skyrocketing test costs. Nanometer technologies will only add to the challenge