Testability Trade-Offs for BIST Data Paths

Authors:
Nicola Nicolici;Bashir M. Al-Hashimi
Affiliations:
Computer-Aided Design and Test Group, Department of Electrical & Computer Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada. nicola@ece.mcmaster.ca WWW: http ...;Electronic Systems Design Group, Department of Electronics and Computer Science, University of Southampton, Southampton SO17 1BJ, U.K. bmah@ecs.soton.ac.uk WWW: http://www.ec ...
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2004

Citing 20
Cited 0

Test Scheduling and Control for VLSI Built-in Self-Test

IEEE Transactions on Computers
Power minimization in IC design: principles and applications

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multiobjective heuristic search in AND/OR graphs

Journal of Algorithms
Scheduling tests for VLSI systems under power constraints

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ATPG for heat dissipation minimization during scan testing

DAC '97 Proceedings of the 34th annual Design Automation Conference
ATPG for Heat Dissipation Minimization During Test Application

IEEE Transactions on Computers
Power management in high-level synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of system-on-a-chip test access architectures under place-and-route and power constraints

Proceedings of the 37th Annual Design Automation Conference
A survey of design techniques for system-level dynamic power management

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Scan latch partitioning into multiple scan chains for power minimization in full scan sequential circuits

DATE '00 Proceedings of the conference on Design, automation and test in Europe
Low Power BIST by Filtering Non-Detecting Vectors

Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Minimized Power Consumption for Scan-Based BIST

Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Guest Editors' Introduction: Tough Challenges as Design and Test Go Nanometer

Computer
Optimal Vector Selection for Low Power BIST

DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems

ATS '99 Proceedings of the 8th Asian Test Symposium
The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power Constraints

VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Low Power Testing of VLSI Circuits: Problems and Solutions

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Power-Conscious Test Synthesis and Scheduling

IEEE Design & Test
Techniques for minimizing power dissipation in scan and combinational circuits during test application

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BIST hardware synthesis for RTL data paths based on test compatibility classes

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Power dissipation during test application is an emerging problem due to yield and reliability concerns. This paper focuses on BIST for RTL data paths and discusses testability trade-offs in terms of test application time, BIST area overhead and power dissipation.