Minimized Power Consumption for Scan-Based BIST

Authors:
Stefan Gerstendörfer;Hans-Joachim Wunderlich
Affiliations:
Computer Architecture Lab, University of Stuttgart, Breitwiesenstr. 20-22, 70565 Stuttgart, Germany. sgersten@informatik.uni-stuttgart.de;Computer Architecture Lab, University of Stuttgart, Breitwiesenstr. 20-22, 70565 Stuttgart, Germany. wu@informatik.uni-stuttgart.de
Venue:
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Year:
2000

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Abstract

Power consumption of digital systems may increasesignificantly during testing. In this paper, systems equipped with ascan-based built-in self-test like the STUMPS architecture areanalyzed, the modules and modes with the highest power consumptionare identified, and design modifications to reduce power consumptionare proposed. The design modifications include some gating logic formasking the scan path activity during shifting, and the synthesis ofadditional logic for suppressing random patterns which do notcontribute to increase the fault coverage. These design changesreduce power consumption during BIST by several orders of magnitude,at very low cost in terms of area and performance.