Power Dissipation During Testing: Should We Worry About it?

Minimized Power Consumption for Scan-Based BIST

Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999

Survey of Low-Power Testing of VLSI Circuits

IEEE Design & Test

Low Power BIST Design by Hypergraph Partitioning: Methodology and Architectures

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Low Power Testing of VLSI Circuits: Problems and Solutions

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design

Minimized Power Consumption For Scan-Based Bist

ITC '99 Proceedings of the 1999 IEEE International Test Conference

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability