Mixed-Mode BIST Using Embedded Processors

Mixed-Mode BIST Using Embedded Processors

Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing

Embedded hardware and software self-testing methodologies for processor cores

Proceedings of the 37th Annual Design Automation Conference

Minimized Power Consumption for Scan-Based BIST

Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999

Deterministic software-based self-testing of embedded processor cores

Proceedings of the conference on Design, automation and test in Europe

Selective-run built-in self-test using an embedded processor

Proceedings of the 12th ACM Great Lakes symposium on VLSI

Embedded software-based self-testing for SoC design

Proceedings of the 39th annual Design Automation Conference

Test of future system-on-chips

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor

Journal of Electronic Testing: Theory and Applications

An algorithmic approach to optimizing fault coverage for BIST logic synthesis

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Accumulator based deterministic BIST

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Characteristic faults and spectral information for logic BIST

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Methods to reduce test application time for accumulator-based self-test

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium

Using BIST Control for Pattern Generation

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Minimized Power Consumption For Scan-Based Bist

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Test data compression and test time reduction using an embedded microprocessor

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power

Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium

Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST

IEEE Transactions on Computers

Software-based self-test of processors under power constraints

Proceedings of the conference on Design, automation and test in Europe: Proceedings

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

Deterministic test vector compression / decompression using an embedded processor

EDCC'05 Proceedings of the 5th European conference on Dependable Computing

Using implications to choose tests through suspect fault identification

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems