Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Using embedded FPGAs for SoC yield improvement
Proceedings of the 39th annual Design Automation Conference
Roundtable: Adding Reconfigurable Logic to SOC Designs
IEEE Design & Test
Mixed-Mode BIST Using Embedded Processors
Proceedings of the IEEE International Test Conference on Test and Design Validity
Deterministic BIST with multiple scan chains
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A hybrid ASIC and FPGA architecture
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A ROMless LFSR Reseeding Scheme for Scan-based BIST
ATS '02 Proceedings of the 11th Asian Test Symposium
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
BIST-Aided Scan Test - A New Method for Test Cost Reduction
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Application of Deterministic Logic BIST on Industrial Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Packet-Based Input Test Data Compression Techniques
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Optimal BIST Using an Embedded Microprocessor
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Efficient Test Data Decompression for System-on-a-Chip Using an Embedded FPGA Core
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Bit-fixing in pseudorandom sequences for scan BIST
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A cocktail approach on random access scan toward low power and high efficiency test
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
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In this paper, a novel hybrid built-in self-test (BIST)approach for system-on-a-chip (SOC) test using anembedded FPGA core is presented. The hybrid BISTcombining pseudorandom test with deterministic test canachieve not only complete fault coverage but also minimaltest cost by selecting the appropriate number ofpseudorandom patterns. Most importantly, theFPGA-based hybrid BIST has minimal hardware overhead,since after testing, the FPGA core can be reconfigured asnormal mission logic. Experimental results for ISCAS 89benchmarks and a platform FPGA chip have proven theefficiency of the proposed approach.