Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A Hardware Architecture for Integrated-Security Services
Transactions on Computational Science IV
FPGA based distributed self healing architecture for reusable systems
Cluster Computing
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In this paper, a novel compression/decompression test approach for system-on-a-chip (SoC) test using an embedded FPGA core is presented. The approach employing Huffman coding achieves test data volume and test application time reduction. The approach makes effective use of the embedded FPGA core such that the implementation is more efficient than that of the embedded processor-based approach. Due to the reconfigurable capability of FPGA, the implementation of this approach has zero hardware overhead and higher flexibility in comparison with the general hardware-based implementation. Since the application with FPGA has the common problems of low speed and high power consumption, we demonstrate how to apply CAM-based (content-addressable-memory) decompression architecture and low-power scan test vectors to overcome the difficulties. It is proven that the proposed approach is efficient from the experimental results.