Selective-run built-in self-test using an embedded processor
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Using embedded FPGAs for SoC yield improvement
Proceedings of the 39th annual Design Automation Conference
A highly regular multi-phase reseeding technique for scan-based BIST
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A scan BIST generation method using a markov source and partial bit-fixing
Proceedings of the 40th annual Design Automation Conference
Test data compression and test time reduction using an embedded microprocessor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
A BIST Pattern Generator Design for Near-Perfect Fault Coverage
IEEE Transactions on Computers
Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
XPAND: An Efficient Test Stimulus Compression Technique
IEEE Transactions on Computers
Column-matching based mixed-mode test pattern generator design technique for BIST
Microprocessors & Microsystems
Analytical approach for testing linking-with-light circuits and systems
IMACS'08 Proceedings of the 7th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems
WSEAS Transactions on Circuits and Systems
Improving linear test data compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Genetic algorithm for test pattern generator design
Applied Intelligence
Overcoming post-silicon validation challenges through quick error detection (QED)
Proceedings of the Conference on Design, Automation and Test in Europe
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A low-overhead scheme for achieving complete (100%) fault coverage during built-in self test of circuits with scan is presented. It does not require modifying the function logic and does not degrade system performance (beyond using scan). Deterministic test cubes that detect the random-pattern-resistant (r.p.r.) faults are embedded in a pseudorandom sequence of bits generated by a linear feedback shift register (LFSR). This is accomplished by altering the pseudorandom sequence by adding logic at the LFSR's serial output to “fix” certain bits. A procedure for synthesizing the bit-fixing logic for embedding the test cubes is described. Experimental results indicate that complete fault coverage can be obtained with low hardware overhead. Further reduction in overhead is possible by using a special correlating automatic test pattern generation procedure that is described for finding test cubes for the r.p.r. faults in a way that maximizes bitwise correlation