Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Evolutionary algorithms in theory and practice: evolution strategies, evolutionary programming, genetic algorithms
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Genetic algorithms for VLSI design, layout & test automation
Genetic algorithms for VLSI design, layout & test automation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Diagnosis Strategies for Hardware or Software Systems
Journal of Electronic Testing: Theory and Applications
Fast and Low-Area TPGs Based on T-Type Flip-Flops can be Easily Integrated to the Scan Path
ETW '00 Proceedings of the IEEE European Test Workshop
A Genetic Algortithm for Automatic Generation of Test Logic for Digital Circuits
ICTAI '96 Proceedings of the 8th International Conference on Tools with Artificial Intelligence
Evolutionary Algorithms for Embedded System Design
Evolutionary Algorithms for Embedded System Design
An Evolutionary Approach to the Design of On-Chip Pseudorandom Test Pattern Generators
Proceedings of the conference on Design, automation and test in Europe
A genetic algorithm-based system for generating test programs for microprocessor IP cores
ICTAI '00 Proceedings of the 12th IEEE International Conference on Tools with Artificial Intelligence
Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor
Journal of Electronic Testing: Theory and Applications
How to Solve It: Modern Heuristics
How to Solve It: Modern Heuristics
Genetic algorithms: the philosopher's stone or an effective solution for high-level TPG?
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
A comparative study of stochastic optimization methods in electric motor design
Applied Intelligence
Pseudo-Random Pattern Generator Design for Column-Matching BIST
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Deterministic Built-in TPG with Segmented FSMs
IOLTS '08 Proceedings of the 2008 14th IEEE International On-Line Testing Symposium
An artificial intelligence approach to the efficiency improvement of a universal motor
Engineering Applications of Artificial Intelligence
Evolution of self-diagnosing hardware
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Bit-fixing in pseudorandom sequences for scan BIST
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Production scheduling with a memetic algorithm
International Journal of Innovative Computing and Applications
MatPort – online mathematics learning with a bioinspired decision-making system
International Journal of Innovative Computing and Applications
Guided restarting local search for production planning
Engineering Applications of Artificial Intelligence
Solving Japanese nonograms by Taguchi-based genetic algorithm
Applied Intelligence
GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
Cell assignment in hybrid CMOS/nanodevices architecture using Tabu Search
Applied Intelligence
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The paper describes an approach for the generation of a deterministic test pattern generator logic, which is composed of D-type and T-type flip-flops. This approach employs a genetic algorithm that searches for an acceptable practical solution in a large space of possible implementations. In contrast to conventional approaches the proposed one reduces the gate count of a built-in self-test structure by concurrent optimization of multiple parameters that influence the final solution. The optimization includes the search for: the optimal combination of register cells type; the presence of inverters at inputs and outputs; the test patterns order in the generated test sequence; and the bit order of test patterns. Results of benchmark experiments and comparison with similar studies demonstrate the efficiency of the proposed evolutionary approach.