A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor
Journal of Electronic Testing: Theory and Applications
Test Pattern Generator Design Optimization Based on Genetic Algorithm
IEA/AIE '08 Proceedings of the 21st international conference on Industrial, Engineering and Other Applications of Applied Intelligent Systems: New Frontiers in Applied Artificial Intelligence
Genetic algorithm for test pattern generator design
Applied Intelligence
Deterministic test pattern generator design
Evo'08 Proceedings of the 2008 conference on Applications of evolutionary computing
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A new structure of the fast and low-area test pattern generator (TPG) composed of T-type flip-flops that can be easily integrated to the scan path is proposed in the paper. Nowadays, techniques of incorporating TPGs containing T-type flip-flops to the scan path either use asynchronous set and reset inputs of flip-flops or require adding a large amount of logic to transform TPG into the shift register. They all introduce large area overhead and degrade timing parameters of TPG. The area overhead of a new TPG structure is much less than in the case of today's existing solutions. Moreover, it posses better timing parameters than conventionally designed TPGs. This last feature has been partially achieved due to the use of dedicated T-type flip-flop, which design is comprised in the paper. In addition, authors propose a testing method that is suitable for verifying correct functioning of both the scan-path and the new type TPGs incorporated in it.