Condensed Linear Feedback Shift Register (LFSR) Testing A Pseudoexhaustive Test Technique
IEEE Transactions on Computers - The MIT Press scientific computation series
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Cellular automata circuits for built-in self test
IBM Journal of Research and Development
Cellular scan test generation for sequential circuits
EURO-DAC '92 Proceedings of the conference on European design automation
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Efficient random testing with global weights
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Exhaustive Test Pattern Generation Using Cyclic Codes
IEEE Transactions on Computers
Calculatoin of Multiple Sets of Weights for Weighted-Random Testing
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Generation of Optimized Single Distributions of Weights for Random Built-in Self-Test
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Logic Test Pattern Generation Using Linear Codes
IEEE Transactions on Computers
Exhaustive Test Pattern Generation with Constant Weight Vectors
IEEE Transactions on Computers
IEEE Design & Test
Fast and Low-Area TPGs Based on T-Type Flip-Flops can be Easily Integrated to the Scan Path
ETW '00 Proceedings of the IEEE European Test Workshop
On Using Deterministic Test Sets in BIST
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
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The paper presents a design method for Built-In Self Test (BIST) that uses a cellular automaton (CA) for test pattern generation. We have extensively studied the quality of generated patterns and we have found several interesting properties of them. The first possibility how to use the CA is to generate pseudoexhaustive test sets as the CA can generate code words of codes with higher minimal code distance of the dual code. There is no need of reseeding the CA in order to generate all the code words. This type of test set can be advantageously used for testing with low number of inputs and low size of cones in the circuits under test (CUT). The proposed CA can also generate weighted random patterns with different global weights which can be used instead of linear feedback shift register (LFSR) pseudorandom sequences, the fault coverage is higher. It can also be used as deterministic pattern compactor in mixed mode testing. The generated sequence can be also easily used for testing CUTs with input-oriented weighted random patterns. The CA is formed by T flip-flops and does not contain any additional logic in the feedback. We proposed a new scheme of BIST where the CA is a part of a modified scan chain. Several experiments were done with ISCAS 85 and 89 benchmark circuits. We compared the quality of the generated test patterns with the quality of the patterns generated in an LFSR.