Efficient random testing with global weights
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Algorithms to compute bridging fault coverage of IDDQ test sets
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Cellular Automata for Weighted Random Pattern Generation
IEEE Transactions on Computers
On-Chip Weighted Random Patterns
Journal of Electronic Testing: Theory and Applications
Improving the test quality for scan-based BIST using a general test application scheme
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Distributed Generation of Weighted Random Patterns
IEEE Transactions on Computers
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Characteristic faults and spectral information for logic BIST
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Fast fault simulation for BIST applications
ATS '95 Proceedings of the 4th Asian Test Symposium
Deterministic Pattern Generation for Weighted Random Pattern Testing
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Methods to reduce test application time for accumulator-based self-test
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
10.3 Distributed Generation of Weighted Random Patterns
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A New Multiple Weight Set Calculation Algorithm
ITC '01 Proceedings of the 2001 IEEE International Test Conference
On Using Machine Learning for Logic BIST
ITC '97 Proceedings of the 1997 IEEE International Test Conference
A BIST Pattern Generator Design for Near-Perfect Fault Coverage
IEEE Transactions on Computers
Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST
IEEE Transactions on Computers
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Design of an efficient weighteld random pattern generation system
ITC'94 Proceedings of the 1994 international conference on Test
Fixed-biased pseudorandom built-in self-test for random pattern resistant circuits
ITC'94 Proceedings of the 1994 international conference on Test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Weighted pseudorandom hybrid BIST
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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