A structure and technique for pseudorandom-based testing of sequential circuits
Journal of Electronic Testing: Theory and Applications
Acceleration techniques for dynamic vector compaction
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Dynamic state traversal for sequential circuit test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient spectral techniques for sequential ATPG
Proceedings of the conference on Design, automation and test in Europe
Mixed-Mode BIST Using Embedded Processors
Proceedings of the IEEE International Test Conference on Test and Design Validity
On Using Machine Learning for Logic BIST
Proceedings of the IEEE International Test Conference
Calculatoin of Multiple Sets of Weights for Weighted-Random Testing
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Accumulator based deterministic BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Fixed-Biased Pseudorandom Built-In Self-Test for Random-Pattern-Resistant Circuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
On Calculating Efficient LFSR Seeds for Built-In Self Test
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
Generating deterministic unordered test patterns with counters
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
DEFUSE: A Deterministic Functional Self-Test Methodology for Processors
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
A novel pattern generator for near-perfect fault-coverage
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Arithmetic built-in self-test for DSP cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST
IEEE Transactions on Computers
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We present a new method of built-in-self-test (BIST) for sequential circuits and system-on-a-chip (SOC) using characteristic faults and circuitspecific spectral information in the form of one or more Hadamard coefficients. The Hadamard coefficients are extracted from the test sequences for a small set of characteristic faults of the circuit. By extracting a few characteristic faults from the circuit, we show that detection of these characteristic faults is sufficient in detecting a vast majority of the remaining faults in the circuit. The small number of characteristic faults allows us to reduce the coefficients necessary for BIST. State relaxation is performed on the compacted test sequences to reduce the spectral noise further. Since we are targeting only a very small number of characteristic faults, the execution times for computing the spectra are greatly reduced. Our experimental results show that our new method can achieve high BIST coverage with both lower computational efforts and storage, with very few characteristic faults.