An Accumulator-Based BIST Approach for Two-Pattern Testing
Journal of Electronic Testing: Theory and Applications
Embedded hardware and software self-testing methodologies for processor cores
Proceedings of the 37th Annual Design Automation Conference
Deterministic software-based self-testing of embedded processor cores
Proceedings of the conference on Design, automation and test in Europe
Testing for interconnect crosstalk defects using on-chip embedded processor cores
Proceedings of the 38th annual Design Automation Conference
Selective-run built-in self-test using an embedded processor
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Test of future system-on-chips
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
Journal of Electronic Testing: Theory and Applications
Characteristic faults and spectral information for logic BIST
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Test data compression and test time reduction using an embedded microprocessor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores
Journal of Electronic Testing: Theory and Applications
Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST
IEEE Transactions on Computers
An efficient architecture for accumulator-based test generation of SIC pairs
Microelectronics Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Error Rate Estimation for Defective Circuits via Ones Counting
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.04 |
A new built-in self-test (BIST) methodology is presented in which all generation and compaction functions are executed by basic building blocks such as adders, ALU's, and multipliers, performing regular arithmetic functions in digital signal processing (DSP) cores. It is demonstrated how these components are themselves tested, and subsequently used to perform more complex testing functions. The need for extra hardware is either entirely eliminated or drastically reduced, test vectors can be easily distributed to different modules of the system, test responses can be collected in parallel, and there is virtually no performance degradation. As an integral part of the proposed BIST environment, arithmetic two-dimensional (2-D) generators of pseudorandom test vectors are also introduced to further integrate the scheme with parallel scan and boundary scan designs used to test peripheral devices of the core