Embedded hardware and software self-testing methodologies for processor cores

Authors:
Li Chen;Sujit Dey;Pablo Sanchez;Krishna Sekar;Ying Cheng
Affiliations:
Dept. of ECE, University of California at San Diego, La Jolla, CA;Dept. of ECE, University of California at San Diego, La Jolla, CA;Dept. of Electronic Technology and System Engineering (TEISA), University of Cantabria, Santander, Spain;Dept. of ECE, University of California at San Diego, La Jolla, CA;Dept. of ECE, University of California at San Diego, La Jolla, CA
Venue:
Proceedings of the 37th Annual Design Automation Conference
Year:
2000

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Abstract

At-speed testing of GHz processors using external testers may not be technically and economically feasible. Hence, there is an emerging need for low-cost, high-quality self-test methodologies, which can be used by processors to test themselves at-speed. Currently, Built-In Self-Test (BIST) is the primary self-test methodology available and is widely used for testing embedded memory cores. In this paper, we report our experiences in applying a commercial BIST methodology to two processor cores and analyze the problems associated with the current hardware-based BIST methodologies. We propose a new software-based self-testing methodology for processors, which uses a software tester embedded in the processor memory as a vehicle for applying structural tests. The software tester consists of programs for test generation and test application. Prior to the test, structural tests are prepared for processor components in the form of self-test signatures. During the process of self-test, the test generation program expands the self-test signatures into test sets, and the test application program applies the tests to the components-under-test at the speed of the processor. Application of the novel software-based self-test method demonstrates its significant cost/fault coverage benefits and its ability to apply at-speed test while alleviating the need for high-speed testers.