Arithmetic built-in self-test for embedded systems

An IEEE 1149.1 Compliant Test Control Architecture

Journal of Electronic Testing: Theory and Applications

An Accumulator-Based BIST Approach for Two-Pattern Testing

Journal of Electronic Testing: Theory and Applications

Embedded hardware and software self-testing methodologies for processor cores

Proceedings of the 37th Annual Design Automation Conference

Optimal hardware pattern generation for functional BIST

DATE '00 Proceedings of the conference on Design, automation and test in Europe

Embedded Checker Architectures for Cyclic and Low-Cost Arithmetic Codes

Journal of Electronic Testing: Theory and Applications

Deterministic software-based self-testing of embedded processor cores

Proceedings of the conference on Design, automation and test in Europe

On applying the set covering model to reseeding

Proceedings of the conference on Design, automation and test in Europe

Using mission logic for embedded testing

Proceedings of the conference on Design, automation and test in Europe

Testing Schemes for FIR Filter Structures

IEEE Transactions on Computers

Selective-run built-in self-test using an embedded processor

Proceedings of the 12th ACM Great Lakes symposium on VLSI

Hidden Markov Models with Patterns to Learn Boolean Vector Sequences and Application to the Built-In Self-Test for Integrated Circuits

IEEE Transactions on Pattern Analysis and Machine Intelligence

An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths

Journal of Electronic Testing: Theory and Applications

Test of future system-on-chips

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST

Journal of Electronic Testing: Theory and Applications

Power-/Energy Efficient BIST Schemes for Processor Data Paths

IEEE Design & Test

Survey of Low-Power Testing of VLSI Circuits

IEEE Design & Test

On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation

Journal of Systems Architecture: the EUROMICRO Journal

Instruction-Based Self-Testing of Processor Cores

Journal of Electronic Testing: Theory and Applications

Modular logic built-in self-test for IP cores

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Low-Cost On-Line Test for Digital Filters

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

Non-Intrusive BIST for Systems-on-a-Chip

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Test Response Compaction by an Accumulator Behaving as a Multiple Input Non-Linear Feedback Shift Register

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Low Power BIST Design by Hypergraph Partitioning: Methodology and Architectures

ITC '00 Proceedings of the 2000 IEEE International Test Conference

DESIGN OF COMPACTORS FOR SIGNATURE-ANALYZERS IN BUILT-IN SELF-TEST

ITC '01 Proceedings of the 2001 IEEE International Test Conference

An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths

ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design

Low Power Testing of VLSI Circuits: Problems and Solutions

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design

Low Power BIST for Wallace Tree-Based Fast Multipliers

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design

Testing strategies for networks on chip

Networks on chip

Test data compression and test time reduction using an embedded microprocessor

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power

Low-Cost Software-Based Self-Testing of RISC Processor Cores

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Aliasing Probability Calculations for Arbitrary Compaction under Independently Selected Random Test Vectors

IEEE Transactions on Computers

Agent-based test and repair of distributed systems

Journal of Embedded Computing - Low-power Embedded Systems

Accumulator-based pseudo-exhaustive two-pattern generation

Journal of Systems Architecture: the EUROMICRO Journal

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

An efficient architecture for accumulator-based test generation of SIC pairs

Microelectronics Journal

Accumulator-based test generation for robust sequential fault testing in DSP cores in near-optimal time

IEEE Transactions on Very Large Scale Integration (VLSI) Systems