Discrete-time signal processing
Discrete-time signal processing
Algorithm-Based Fault Detection for Signal Processing Applications
IEEE Transactions on Computers
New Fault Tolerant Techniques for Residue Number Systems
IEEE Transactions on Computers
Arithmetic built-in self-test for embedded systems
Arithmetic built-in self-test for embedded systems
Towards 100% Testable FIR Digital Filters
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
R-CBIST: an effective RAM-based input vector monitoring concurrent BIST technique
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Versatile BIST: an integrated approach to on-line/off-line BIST
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Parameterizable Testing Scheme for FIR Filters
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Low Cost Concurrent Test Implementation for Linear Digital Systems
ETW '00 Proceedings of the IEEE European Test Workshop
SPaRe: Selective Partial Replication for Concurrent Fault Detection in FSMs
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Design of concurrent test hardware for linear analog circuits with constrained hardware overhead
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A low-cost on-line test scheme for digital filters is proposed. The scheme uses an invariant of the digital filter, the frequency response at specific points, in order to detect possible malfunctioning of the circuit. The analysis performed indicates that 100% fault secureness is possible, if certain design constraints are followed.