IEEE Transactions on Computers
A Fault-Tolerant FFT Processor
IEEE Transactions on Computers
The algebraic eigenvalue problem
The algebraic eigenvalue problem
Digital image processing
Fault-secure algorithms for multiple-processor systems
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
A novel approach to system-level fault tolerance in hypercube multiprocessors
C3P Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1
IEEE Transactions on Software Engineering
Compiler-Assisted Synthesis of Algorithm-Based Checking in Multiprocessors
IEEE Transactions on Computers
Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor
IEEE Transactions on Computers
Algorithm-Based Fault Tolerant Synthesis for Linear Operations
IEEE Transactions on Computers
New Encoding/Decoding Methods for Designing Fault-Tolerant Matrix Operations
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Computers
Concurrent Error Detection in Nonlinear Digital Circuits Using Time-Freeze Linearization
IEEE Transactions on Computers
Safety and Reliability Driven Task Allocation in Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
Optimal Design of Checks for Error Detection and Location in Fault-Tolerant Multiprocessor Systems
IEEE Transactions on Computers
The Design of Fault-Tolerant Linear Digital State Variable Systems: Theory and Techniques
IEEE Transactions on Computers
Diagnosability and Diagnosis of Algorithm-Based Fault-Tolerant Systems
IEEE Transactions on Computers
Algorithm-Based Fault Tolerance for FFT Networks
IEEE Transactions on Computers
An Efficient Algorithm-Based Concurrent Error Detection for FFT Networks
IEEE Transactions on Computers
A New Error Analysis Based Method for Tolerance Computation for Algorithm-Based Checks
IEEE Transactions on Computers
A Novel Concurrent Error Detection Scheme for FFT Networks
IEEE Transactions on Parallel and Distributed Systems
Synthesis of Algorithm-Based Fault-Tolerant Systems from Dependence Graphs
IEEE Transactions on Parallel and Distributed Systems
Partitioned Encoding Schemes for Algorithm-Based Fault Tolerance in Massively Parallel Systems
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
Fault-Detection by Result-Checking for the Eigenproblem
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Self-checking architectures for fast Hartley transform
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Low Cost Concurrent Test Implementation for Linear Digital Systems
ETW '00 Proceedings of the IEEE European Test Workshop
Cost analysis of a new algorithmic-based soft-error tolerant architecture
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Low-Cost On-Line Test for Digital Filters
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Analytical Redundancy Based Approach for Concurrent Fault Detection in Linear Digital Systems
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Feasibility and Effectiveness of the Algorithm for Overhead Reduction in Analog Checkers
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
On-Line Fault Detection In DSP Circuits Using Extrapolated Checksums with Minimal Test Points
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An Algorithm-Based Error Detection Scheme for the Multigrid Method
IEEE Transactions on Computers
Fault Tolerance Techniques for the Merrimac Streaming Supercomputer
SC '05 Proceedings of the 2005 ACM/IEEE conference on Supercomputing
Fault Tolerance Analysis of Communication System Interleavers: the 802.11a Case Study
Journal of Signal Processing Systems
Integration, the VLSI Journal
Nonconcurrent error correction in the presence of roundoff noise
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Checksum-based probabilistic transient-error compensation for linear digital systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient soft error-tolerant adaptive equalizers
IEEE Transactions on Circuits and Systems Part I: Regular Papers
On concurrent error location and correction of FFT networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 15.02 |
The increasing demands for high-performance signal processing along with the availability of inexpensive high-performance processors have results in numerous proposals for special-purpose array processors for signal processing applications. A functional-level concurrent error-detection scheme is presented for such VLSI signal processing architectures as those proposed for the FFT and QR factorization. Some basic properties involved in such computations are used to check the correctness of the computed output values. This fault-detection scheme is shown to be applicable to a class of problems rather than a particular problem, unlike the earlier algorithm-based error-detection techniques. The effects of roundoff/truncation errors due to finite-precision arithmetic are evaluated. It is shown that the error coverage is high with large word sizes.