IEEE Transactions on Computers
An analysis of algorithm-based fault tolerance techniques
Journal of Parallel and Distributed Computing
Discrete-time signal processing
Discrete-time signal processing
Real-Number Codes for Fault-Tolerant Matrix Operations on Processor Arrays
IEEE Transactions on Computers
Compiler-Assisted Synthesis of Algorithm-Based Checking in Multiprocessors
IEEE Transactions on Computers
Algorithm-Based Fault Detection for Signal Processing Applications
IEEE Transactions on Computers
Digital Signal Processing
Digital Control Systems
VLSI Signal Processing; A Bit-Serial Approach
VLSI Signal Processing; A Bit-Serial Approach
Algorithm-Based Fault Tolerant Synthesis for Linear Operations
IEEE Transactions on Computers
Concurrent Error Detection in Nonlinear Digital Circuits Using Time-Freeze Linearization
IEEE Transactions on Computers
Analytical Redundancy Based Approach for Concurrent Fault Detection in Linear Digital Systems
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Feasibility and Effectiveness of the Algorithm for Overhead Reduction in Analog Checkers
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
On-Line Fault Detection In DSP Circuits Using Extrapolated Checksums with Minimal Test Points
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Integration, the VLSI Journal
Nonconcurrent error correction in the presence of roundoff noise
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Checksum-based probabilistic transient-error compensation for linear digital systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A theory for error detection in linear digital state variable systems is described. With the aid of a tool called the gain matrix, it is shown that the effect of error propagation along different paths of the circuit can be analyzed. For circuits with operator fanout, it is shown that despite the fact that single faulty operators cause multiple state variables to be erroneous, no more additional check variables are required than for circuits without operator fanout. It is further shown that hardware optimization can be performed by sharing hardware functions between the original state variable system and its error detection circuitry. The analysis is performed for both single and multiple faulty operators. A scheme for error correction that performs error correction in real time is proposed. Experimental results that illustrate the practical viability of the proposed scheme are discussed.