IEEE Transactions on Computers
An analysis of algorithm-based fault tolerance techniques
Journal of Parallel and Distributed Computing
Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Real-Number Codes for Fault-Tolerant Matrix Operations on Processor Arrays
IEEE Transactions on Computers
Algorithm-Based Fault Detection for Signal Processing Applications
IEEE Transactions on Computers
Concurrent Error Detection in Nonlinear Digital Circuits Using Time-Freeze Linearization
IEEE Transactions on Computers
Soft digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Reliable and energy-efficient digital signal processing
Proceedings of the 39th annual Design Automation Conference
Advanced Digital Signal Processing: Theory and Applications
Advanced Digital Signal Processing: Theory and Applications
Coding Theory: The Essentials
VLSI Signal Processing; A Bit-Serial Approach
VLSI Signal Processing; A Bit-Serial Approach
Convergence Properties of the Nelder--Mead Simplex Method in Low Dimensions
SIAM Journal on Optimization
The Design of Fault-Tolerant Linear Digital State Variable Systems: Theory and Techniques
IEEE Transactions on Computers
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
Energy-efficient soft error-tolerant digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Probabilistic Compensation for Digital Filters Using Pervasive Noise-Induced Operator Errors
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Probabilistic Concurrent Error Compensation in Nonlinear Digital Filters Using Linearized Checksums
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
Algorithm-Based Fault Tolerance for Matrix Operations
IEEE Transactions on Computers
Analysis and Evaluation of a New Algorithm Based Fault Tolerance for Computing Systems
International Journal of Grid and High Performance Computing
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In this paper, a probabilistic compensation technique for minimizing the effect of transient errors effect is proposed. The focus is to develop a compensation technique for DSP applications in which exact error compensation is not necessary and end-to-end system level performance is degraded minimally as long as the impact of the "noise" injected into the system by the transient errors is minimized. The proposed technique, called checksum-based probabilistic compensation, uses real-number checksum codes for error detection and partial compensation. Traditional coding techniques need a code of distance three and relatively complex calculations for perfect error correction. Here, it is shown that a distance-two code can be used to perform probabilistic error compensation in linear systems with the objective of improving the signal-to-noise ratio in the presence of random transient errors. The goal is to have a technique with small power and area overhead and to perform compensation in real time with negligible latency. The proposed technique is comprehensive and can handle errors in the combinational circuitry and storage elements. Comparison against a system with no error correction shows that up to 13-dB SNR improvement is possible. The area, power, and timing overheads of the proposed technique are analyzed.