Accumulation of Round-Off Error in Fast Fourier Transforms
Journal of the ACM (JACM)
A reconfigurable and fault-tolerant VLSI multiprocessor array
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Fault-secure algorithms for multiple-processor systems
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Real-Number Codes for Fault-Tolerant Matrix Operations on Processor Arrays
IEEE Transactions on Computers
Algorithm-Based Fault Detection for Signal Processing Applications
IEEE Transactions on Computers
Algorithm-Based Error-Detection Schemes for Iterative Solution of Partial Differential Equations
IEEE Transactions on Computers
Algorithm-Based Fault Tolerant Synthesis for Linear Operations
IEEE Transactions on Computers
New Encoding/Decoding Methods for Designing Fault-Tolerant Matrix Operations
IEEE Transactions on Parallel and Distributed Systems
Algorithm-Based Fault Location and Recovery for Matrix Computations on Multiprocessor Systems
IEEE Transactions on Computers
IEEE Transactions on Computers
Concurrent Error Detection in Nonlinear Digital Circuits Using Time-Freeze Linearization
IEEE Transactions on Computers
Efficient FFT network testing and diagnosis schemes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploiting Redundancy to Speed Up Parallel Systems
IEEE Parallel & Distributed Technology: Systems & Technology
DC Built-In Self-Test for Linear Analog Circuits
IEEE Design & Test
Optimal Design of Checks for Error Detection and Location in Fault-Tolerant Multiprocessor Systems
IEEE Transactions on Computers
The Design of Fault-Tolerant Linear Digital State Variable Systems: Theory and Techniques
IEEE Transactions on Computers
Diagnosability and Diagnosis of Algorithm-Based Fault-Tolerant Systems
IEEE Transactions on Computers
Error Correcting Codes Over Z/sub 2(m/) for Algorithm-Based Fault Tolerance
IEEE Transactions on Computers
IEEE Transactions on Computers
Algorithm-Based Fault Tolerance for FFT Networks
IEEE Transactions on Computers
An Efficient Algorithm-Based Concurrent Error Detection for FFT Networks
IEEE Transactions on Computers
A Novel Concurrent Error Detection Scheme for FFT Networks
IEEE Transactions on Parallel and Distributed Systems
Synthesis of Algorithm-Based Fault-Tolerant Systems from Dependence Graphs
IEEE Transactions on Parallel and Distributed Systems
Partitioned Encoding Schemes for Algorithm-Based Fault Tolerance in Massively Parallel Systems
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
Concurrent Error Detection in Fast Unitary Transform Algorithms
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
Self-checking architectures for fast Hartley transform
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Cost analysis of a new algorithmic-based soft-error tolerant architecture
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Low-cost DC built-in self-test of linear analog circuits using checksums
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Optimal Design of Checksum-Based Checkers for Fault Detection in Linear Analog Circuits
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Analytical Redundancy Based Approach for Concurrent Fault Detection in Linear Digital Systems
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
On-Line Fault Detection In DSP Circuits Using Extrapolated Checksums with Minimal Test Points
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An Algorithm-Based Error Detection Scheme for the Multigrid Method
IEEE Transactions on Computers
Concurrent Error Detection in Wavelet Lifting Transforms
IEEE Transactions on Computers
Fault Tolerance Techniques for the Merrimac Streaming Supercomputer
SC '05 Proceedings of the 2005 ACM/IEEE conference on Supercomputing
Sequential element design with built-in soft error resilience
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Checksum-based probabilistic transient-error compensation for linear digital systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Stochastic networked computation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design-for-testability and fault-tolerant techniques for FFT processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On concurrent error location and correction of FFT networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 15.03 |
Two concurrent error detection (CED) schemes are proposed for N-point fast Fourier transform (FFT) networks that consists of log/sub 2/N stages with N/2 two-point butterfly modules for each stage. The method assumes that failures are confined to a single complex multiplier or adder or to one input or output set of lines. Such a fault model covers a broad class of faults. It is shown that only a small overhead ratio, O(2/log/sub 2/N) of hardware, is required for the networks to obtain fault-secure results in the first scheme. A novel data retry technique is used to locate the faulty modules. Large roundoff errors can be detected and treated in the same manner as functional errors. The retry technique can also distinguish between the roundoff errors and functional errors that are caused by some physical failures. In the second scheme, a time-redundancy method is used to achieve both error detection and location. It is sown that only negligible hardware overhead is required. However, the throughput is reduced to half that of the original system, without both error detection and location, because of the nature of time-redundancy methods.