Design-for-testability and fault-tolerant techniques for FFT processors

Authors:
Shyue-Kung Lu;Jen-Sheng Shih;Shih-Chang Huang
Affiliations:
Department of Electronic Engineering, Fu-Jen Catholic University, Taipei, Taiwan, R.O.C;Pixelworks, U.S., Taipei, Taiwan, R.O.C and Department of Electronic Engineering, Fu-Jen Catholic University, Taipei Taiwan, R.O.C;Department of Electronic Engineering, Fu-Jen Catholic University, Taipei, Taiwan, R.O.C
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2005

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Abstract

In this paper, we first propose a novel design-for-testability approach based on M-testability conditions for module-level systolic fast Fourier transform (FFT) arrays. Our M-testability conditions guarantee 100% single-module-fault testability with a minimum number of test patterns. Based on this testable design, fault-tolerant approaches at the bit level and the multiply-subtract-add (MSA) module level are proposed, respectively. If the reconfiguration is performed at the bit level, then the FFTBIT network is constructed. Two types of reconfiguration schemes (Type-I FFTMSA and Type-II FFTMSA) are proposed at the MSA module level. Since both the design for testability (DFT) and the design for yield (DFY) issues are considered at the same time for all these proposed approaches, the resulting architectures are simpler as compared with previous works. The reliability of the FFT system increases significantly. The hardware overhead is low--about 12% and 1/2N for the FFTBIT network and the Type-II FFTMSA network, respectively. An experimental chip is also implemented to verify our approaches. Reliabilities and hardware overhead are also evaluated and compared with previous works.