Fault diagnosis in iterative arrays.
Fault diagnosis in iterative arrays.
Fault Detection in Iterative Logic Arrays
IEEE Transactions on Computers
Universal Single Transition Time Asynchronous State Assignments
IEEE Transactions on Computers
Testing for faults in combinational cellular logic arrays
FOCS '67 Proceedings of the 8th Annual Symposium on Switching and Automata Theory (SWAT 1967)
Testability Conditions for Bilateral Arrays of Combinational Cells
IEEE Transactions on Computers
A minimum test set for multiple fault detection on ripple carry adders
IEEE Transactions on Computers
Universal test complexity of field-programmable gate arrays
ATS '95 Proceedings of the 4th Asian Test Symposium
An effective BIST design for PLA
ATS '95 Proceedings of the 4th Asian Test Symposium
A C-testable modified Booth's array multiplier
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Robust Sequential Fault Testing of Iterative Logic Arrays
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Accumulator-based pseudo-exhaustive two-pattern generation
Journal of Systems Architecture: the EUROMICRO Journal
On Modifying Logic Networks to Improve Their Diagnosability
IEEE Transactions on Computers
The Design of Easily Testable VLSI Array Multipliers
IEEE Transactions on Computers
Built-In Testing of One-Dimensional Unilateral Iterative Arrays
IEEE Transactions on Computers
Truth-Table Verification of an Iterative Logic Array
IEEE Transactions on Computers
Recursion and Testing of Combinational Circuits
IEEE Transactions on Computers
A Functional Approach to Testing Bit-Sliced Microprocessors
IEEE Transactions on Computers
A Testable Design of Iterative Logic Arrays
IEEE Transactions on Computers
Design of Easily Testable Bit-Sliced Systems
IEEE Transactions on Computers
Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates
Journal of Electronic Testing: Theory and Applications
Design-for-testability techniques for CORDIC design
Microelectronics Journal
Recursive pseudo-exhaustive two-pattern generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The KARL/KARATE system - automatic test pattern generation based on RT level descriptions
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Design-for-testability and fault-tolerant techniques for FFT processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ALADIN: a multilevel testability analyzer for VLSI system design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic test pattern generation
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
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It has been shown that the number of tests required to detect all faults in a one-dimensional unilateral combinational iterative array consisting of p cells will, in general, be proportional to p. In this paper we consider properties of such systems that enable them to be tested with a fixed constant number of tests independent of p, the number of cells in the system. Such systems are referred to as C-testable. Necessary and sufficient conditions on the basic cell state table are derived for an iterative system to be C-testable. It is shown that an arbitrary N-state cell table can be augmented by the addition of, at most, one row and less than [log2 N]2 columns (for N = 2) so as to be C-testable.