Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
An Effective BIST Scheme for ROM's
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Journal of Electronic Testing: Theory and Applications
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Serial Interfacing for Embedded-Memory Testing
IEEE Design & Test
An Effective BIST Scheme for Ring-Address Type FIFOs
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
An effective BIST scheme for carry-save and carry-propagate array multipliers
ATS '95 Proceedings of the 4th Asian Test Symposium
The Design of Easily Testable VLSI Array Multipliers
IEEE Transactions on Computers
Built-In Testing of One-Dimensional Unilateral Iterative Arrays
IEEE Transactions on Computers
Easily Testable Iterative Systems
IEEE Transactions on Computers
Scan Latch Design for Delay Test
ITC '97 Proceedings of the 1997 IEEE International Test Conference
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In this paper, we describe a new design of built-in self test for programmable logic arrays (PLAs). The idea is to use a simple deterministic test pattern generator to generate test patterns such that each cross point in the AND array can be evaluated one after another. The simplest multiple input signature register which uses X/sup Q/+1 as its characteristic polynomial is used to evaluate the test results, where Q is the number of outputs. The final signature can be further compressed into only ONE bit. Instead of determining the probability of fault detection only, in this design, the fault detection capability is analyzed using the stuck-at fault, and the contact fault models. It is shown that all these modeled faults can be detected. This design is shown to give a better trade-off between the cost and the performance of built-in self test designs for PLAs.