Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
AC strength of a pattern generator
Journal of Electronic Testing: Theory and Applications
Built-in self-test (BIST) design of high-speed carry-free dividers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms
IEEE Transactions on Computers
Overview of PowerPCTM 620 Multiprocessor Verification Strategy
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
At-Speed Test is not Necessarily an AC Test
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Production Experience with Built-In Self-Test in the IBM ES/9000 System
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
The PowerPC 603TM Microprocessor: An Array Built-In Self-Test Mechanism
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Generator choices for delay test
ATS '95 Proceedings of the 4th Asian Test Symposium
An effective BIST design for PLA
ATS '95 Proceedings of the 4th Asian Test Symposium
An effective BIST scheme for carry-save and carry-propagate array multipliers
ATS '95 Proceedings of the 4th Asian Test Symposium
Designing Self-Testable Multi-Chip Modules
EDTC '96 Proceedings of the 1996 European conference on Design and Test
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This paper describes three new designs of a shift registerlatch that lend themselves to distributed self-test and delaytest. The advantages of these new SRLs are faster applicationof test vectors, higher DC and AC fault coverages,with low performance impact. Operation, cost, and otherattributes are studied in detail. Results of adopting one ofthe new SRLs are reported on three pilot chips.