Production Experience with Built-In Self-Test in the IBM ES/9000 System

Reducing the MISR Size

IEEE Transactions on Computers

Salvaging Test Windows in BIST Diagnostics

IEEE Transactions on Computers

Random Pattern Testability of Control and Address Circuitry of an Embedded Memory with Feed-Forward Data-Path Connections

Journal of Electronic Testing: Theory and Applications

Distributed BIST Architecture to Combat Delay Faults

Journal of Electronic Testing: Theory and Applications

On the Maximum Value of Aliasing Probabilities for Single Input Signature Registers

IEEE Transactions on Computers

Aliasing Error for a Mask ROM Built-In Self-Test

IEEE Transactions on Computers

A simple technique for locating gate-level faults in combinational circuits

ATS '95 Proceedings of the 4th Asian Test Symposium

Obtaining High Fault Coverage with Circular BIST Via State Skipping

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium

Scan Latch Design for Delay Test

ITC '97 Proceedings of the 1997 IEEE International Test Conference

CASP: concurrent autonomous chip self-test using stored test patterns

Proceedings of the conference on Design, automation and test in Europe