Logic testing and design for testability
Logic testing and design for testability
Aliasing Probability for Multiple Input Signature Analyzer
IEEE Transactions on Computers
A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression
IEEE Transactions on Computers
Simple Bounds on Serial Signature Analysis Aliasing for Random Testing
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Notes on Multiple Input Signature Analysis
IEEE Transactions on Computers
Improved Yield Models for Fault-Tolerant Memory Chips
IEEE Transactions on Computers
Design of Self-Diagnostic Boards by Multiple Signature Analysis
IEEE Transactions on Computers
Built-In Self-Diagnostic Read-Only-Memories
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Built-In Self-Test for High-Speed Data-Path Circuitry
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Achieving Board-Level BIST Using the Boundary-Scan Master
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Production Experience with Built-In Self-Test in the IBM ES/9000 System
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
LSSD Compatible and Concurrently Testable Ram
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
BIST for Embedded Static RAMs with Coverage Calculation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
An ALU-Based Programmable MISR/Pseudorandom Generator for a MC68HC11 Family Self-Test
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Testability Features of the SuperSPARCtm
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Error Control Coding, Second Edition
Error Control Coding, Second Edition
Experimental fault analysis of 1 Mb SRAM chips
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
| Hi-index | 14.98 |
To develop better ROM BIST techniques we first experimentally surveyed cell faults, word-line faults, bit-line faults, delay faults and other types of faults occurring in 1,000 faulty mask ROM chips. We found that most of the stuck-at faults were within a single mat. We then theoretically analyzed the aliasing probability for a mask ROM containing a fault or faults within a single mat. To experimentally evaluate BIST aliasing errors we implemented six MISRs on a custom board and observed actual aliasing errors. The experimentally measured aliasing probabilities agreed with the probabilities derived theoretically. No aliasing error occurred for the 16-stage, 8-input MISR.