Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A Data Compression Technique for Built-In Self-Test
IEEE Transactions on Computers
Coding and decoding algorithms of Reed-Solomon codes executed on M68000 microprocessor
on Coding theory and applications
Aliasing Probability for Multiple Input Signature Analyzer
IEEE Transactions on Computers
Encyclopedia of Mathematics and Its Applications: The Theory of Information and Coding: A Mathematical Framework for Communication
Shift Register Sequences
Built-In Self-Diagnostic Read-Only-Memories
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Cellular-Automata-Array-Based Diagnosis of Board Level Faults
IEEE Transactions on Computers
Diagnosis of Scan Cells in BIST Environment
IEEE Transactions on Computers
Aliasing Error for a Mask ROM Built-In Self-Test
IEEE Transactions on Computers
Board level fault diagnosis using cellular automata array
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
FAULT DIAGNOSIS IN-SCAN-BASED BIST
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Fault Diagnosis in Scan-Based BIST Using Both Time and Space Information
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Codes
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Journal of Electronic Testing: Theory and Applications
Isolation of Failing Scan Cells through Convolutional Test Response Compaction
Journal of Electronic Testing: Theory and Applications
Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis
IEEE Transactions on Computers
Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs
Journal of Electronic Testing: Theory and Applications
| Hi-index | 14.99 |
A new design approach, based on multiple signature analysis, for self-diagnostic boards is presented. For this approach, test responses from all chips on the board are compressed into space-time signatures using nonbinary multiple error-correcting codes, and faulty chips are identified by analyzing relations between distortions in these signatures. This approach results in a considerable reduction of a hardware overhead, required for diagnostics, as compared with the straightforward approach where separate signatures are computed for each chip on the board. The diagnostic approach presented can also be used for identification of faulty boards in a system or for faulty processors in a multiprocessor environment.