Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Multiple error detection and identification via signature analysis
Journal of Electronic Testing: Theory and Applications
A Tutorial on Built-in Self-Test. I. Principles
IEEE Design & Test
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Design of Self-Diagnostic Boards by Multiple Signature Analysis
IEEE Transactions on Computers
BIST Fault Diagnosis in Scan-Based VLSI Environments
Proceedings of the IEEE International Test Conference on Test and Design Validity
Improving the efficiency of error identification via signature analysis
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Diagnosis of scan path failures
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
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The paper presents a new fault diagnosistechnique for scan-based BIST designs. It can be usedfor non-adaptive identification of the scan cells that aredriven by erroneous signals, irrespective of the errormultiplicity. The proposed scheme employs a simplescan cell selection hardware which in conjunction witha conventional signature analysis allows flexible trade-offsbetween the test application time and the diagnosticresolution.