Diagnosis of Scan Cells in BIST Environment
IEEE Transactions on Computers
A Technique for Fault Diagnosis of Defects in Scan Chains
ITC '01 Proceedings of the 2001 IEEE International Test Conference
FAULT DIAGNOSIS IN-SCAN-BASED BIST
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Diagnosis of Multiple Hold-Time and Setup-Time Faults in Scan Chains
IEEE Transactions on Computers
Quick Scan Chain Diagnosis Using Signal Profiling
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Using fault model relaxation to diagnose real scan chain defects
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Isolation of Failing Scan Cells through Convolutional Test Response Compaction
Journal of Electronic Testing: Theory and Applications
Dynamic learning based scan chain diagnosis
Proceedings of the conference on Design, automation and test in Europe
Diagnosis, modeling and tolerance of scan chain hold-time violations
Proceedings of the conference on Design, automation and test in Europe
A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
S/390 G5 CMOS microprocessor diagnostics
IBM Journal of Research and Development
Scan chain hold-time violations: can they be tolerated
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Diagnosis of single stuck-at faults and multiple timing faults in scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Diagnosing scan clock delay faults through statistical timing pruning
Proceedings of the 48th Design Automation Conference
Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs
Journal of Electronic Testing: Theory and Applications
An ATE assisted DFD technique for volume diagnosis of scan chains
Proceedings of the 50th Annual Design Automation Conference
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Abstract: Scan based diagnostic schemes are used to diagnose faults in faulty circuits. Such techniques assume that the scan path itself is fault-free. However, the logic circuitry associated with the scan chain may occupy nearly 30% of a chip area and hence warrants consideration during fault diagnosis. In this work we propose a simple extension to the scan chain to diagnose faults in scan chains.