IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Failure Diagnosis of Structured VLSI
IEEE Design & Test
High-Accuracy Flush-and-Scan Software Diagnostic
IEEE Design & Test
Diagnosis of Scan Chain Failures
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Failure Analysis for Full-Scan Circuits
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An Efficient Scheme to Diagnose Scan Chains
Proceedings of the IEEE International Test Conference
A technique for fault diagnosis of defects in scan chains
Proceedings of the IEEE International Test Conference 2001
Diagnosis of scan path failures
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Diagnosis of Multiple Hold-Time and Setup-Time Faults in Scan Chains
IEEE Transactions on Computers
Quick Scan Chain Diagnosis Using Signal Profiling
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A Novel Scan Chain Diagnostics Technique Based on Light Emission from Leakage Current
ITC '04 Proceedings of the International Test Conference on International Test Conference
Channel Masking Synthesis for Efficient On-Chip Test Compression
ITC '04 Proceedings of the International Test Conference on International Test Conference
Survey of Test Vector Compression Techniques
IEEE Design & Test
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
Dynamic learning based scan chain diagnosis
Proceedings of the conference on Design, automation and test in Europe
Diagnose Multiple Stuck-at Scan Chain Faults
ETS '08 Proceedings of the 2008 13th European Test Symposium
Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns
ATS '09 Proceedings of the 2009 Asian Test Symposium
Improving compressed test pattern generation for multiple scan chain failure diagnosis
Proceedings of the Conference on Design, Automation and Test in Europe
Enhance Profiling-Based Scan Chain Diagnosis by Pattern Masking
ATS '10 Proceedings of the 2010 19th IEEE Asian Test Symposium
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Volume Diagnosis is extremely important to ramp up the yield during the IC manufacturing process. Limited observability due to test response compaction negatively affects the diagnosis procedure. Hence, in a compaction environment, it is important to implement Design For Diagnosis (DFD) methodology to restore diagnostic resolution. In this paper, a novel DFD technique which makes the faulty chains to behave as good chains during loading, has been proposed. As a result, the errors introduced in the responses, must occur during unloading of the scan chains. Diagnosis can then be performed by directly comparing the actual and expected responses without any fault simulation - leading to significant reduction in time. Results on benchmark circuits show that the average number of suspected cells for single chain failure is 1.27 (ideal value being 1) and the time taken for diagnosis is in the order of milli-seconds.