VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

Survey of Test Vector Compression Techniques

IEEE Design & Test

Critical-path-aware X-filling for effective IR-drop reduction in at-speed scan testing

Proceedings of the 44th annual Design Automation Conference

Parallel fault backtracing for calculation of fault coverage

Proceedings of the 2008 Asia and South Pacific Design Automation Conference

Using reiterative LFSR based X-masking to increase output compression in presence of unknowns

Proceedings of the 18th ACM Great Lakes symposium on VLSI

A design-for-digital-testability circuit structure for Σ-Δ modulators

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing

Journal of Electronic Testing: Theory and Applications

Layout-aware scan chain reorder for launch-off-shift transition test coverage

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Embedded DSP Processor Design: Application Specific Instruction Set Processors

Embedded DSP Processor Design: Application Specific Instruction Set Processors

Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

Fault modeling and testing of retention flip-flops in low power designs

Proceedings of the 2009 Asia and South Pacific Design Automation Conference

A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits

IEICE - Transactions on Information and Systems

A Multi-Code Compression Scheme for Test Time Reduction of System-on-Chip Designs

IEICE - Transactions on Information and Systems

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Scan-chain partition for high test-data compressibility and low shift power under routing constraint

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment

Proceedings of the 2009 International Conference on Computer-Aided Design

BIST design optimization for large-scale embedded memory cores

Proceedings of the 2009 International Conference on Computer-Aided Design

QC-fill: quick-and-cool X-filling for multicasting-based scan test

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Using launch-on-capture for testing BIST designs containing synchronous and asynchronous clock domains

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Search State Compatibility Based Incremental Learning Framework and Output Deviation Based X-filling for Diagnostic Test Generation

Journal of Electronic Testing: Theory and Applications

High volume diagnosis in memory BIST based on compressed failure data

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Multiple scan trees synthesis for test time/data and routing length reduction under output constraint

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Statistical path selection for at-speed test

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Complex oscillation-based test and its application to analog filters

IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS 2009

Fault Modeling and Analysis for Resistive Bridging Defects in a Synchronizer

Journal of Electronic Testing: Theory and Applications

DFT and minimum leakage pattern generation for static power reduction during test and burn-in

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Fast identification of operating current for toggle MRAM by spiral search

Proceedings of the 47th Design Automation Conference

Parallel X-fault simulation with critical path tracing technique

Proceedings of the Conference on Design, Automation and Test in Europe

Diagnosis of multiple arbitrary faults with mask and reinforcement effect

Proceedings of the Conference on Design, Automation and Test in Europe

A robust ADC code hit counting technique

Proceedings of the Conference on Design, Automation and Test in Europe

QC-fill: an X-fill method for quick-and-cool scan test

Proceedings of the Conference on Design, Automation and Test in Europe

Chiba Scan Delay Fault Testing with Short Test Application Time

Journal of Electronic Testing: Theory and Applications

DiSC: a new diagnosis method for multiple scan chain failures

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Construction of SEU tolerant flip-flops allowing enhanced scan delay fault testing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A low overhead high test compression technique using pattern clustering with n-detection test support

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Diagnosis of MRAM write disturbance fault

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Improved delay measurement method in FPGA based on transition probability

Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays

A physical-location-aware fault redistribution for maximum IR-drop reduction

Proceedings of the 16th Asia and South Pacific Design Automation Conference

Pseudorandom Test of Nonlinear Analog and Mixed-Signal Circuits Based on a Volterra Series Model

Journal of Electronic Testing: Theory and Applications

Achieving low capture and shift power in linear decompressor-based test compression environment

Microelectronics Journal

A modified scheme for simultaneous reduction of test data volume and testing power

VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test

Test data compression for noc based socs using binary arithmetic operations

VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains

ACM Transactions on Design Automation of Electronic Systems (TODAES)

An effective two-pattern test generator for Arithmetic BIST

Computers and Electrical Engineering

On-line functionally untestable fault identification in embedded processor cores

Proceedings of the Conference on Design, Automation and Test in Europe

An ATE assisted DFD technique for volume diagnosis of scan chains

Proceedings of the 50th Annual Design Automation Conference

A physical-location-aware X-bit redistribution for maximum IR-drop reduction

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IVF: characterizing the vulnerability of microprocessor structures to intermittent faults

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Online Testable Approaches in Reversible Logic

Journal of Electronic Testing: Theory and Applications