A BIST scheme for on-chip ADC and DAC testing
DATE '00 Proceedings of the conference on Design, automation and test in Europe
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Implementation of a linear histogram BIST for ADCs
Proceedings of the conference on Design, automation and test in Europe
DSP-Based Testing of Analog and Mixed-Signal Circuits
DSP-Based Testing of Analog and Mixed-Signal Circuits
A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST
Proceedings of the IEEE International Test Conference
A BIST Scheme for an SNR Test of a Sigma-Delta ADC
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A Built-in Self- Test for ADC and DAC in a Single-Chip Speech CODEC
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Efficient and accurate testing of analog-to-digital converters using oscillation-test method
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Hardware Resource Minimization for Histogram-Based ADC BIST
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
A Low-Cost Adaptive Ramp Generator for Analog BIST Applications
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
A Self Calibrated ADC BIST Methodology
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Optimal Schemes for ADC BIST Based on Histogram
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
An ADC-BiST scheme using sequential code analysis
Proceedings of the conference on Design, automation and test in Europe
An on-chip solution for static ADC test and measurement
Proceedings of the 19th ACM Great Lakes symposium on VLSI
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This paper presents a robust, low-cost ADC code hit counting technique to record the number of times each ADC output code word appears with respect to the ramp input. Using a smart center code tracking engine, the proposed code hit counter performs robustly against the code transition noise, missing code segments, and non-monotonicity; furthermore, the required hardware and test time is at the same level as the known best results. The robustness together with the low overhead makes the proposed code hit counter suitable for (on-line) ADC self-testing and self-calibration applications.