A BIST scheme for on-chip ADC and DAC testing

  • Authors:
  • Jiun-Lang Huang;Chee-Kian Ong;Kwang-Ting Cheng

  • Affiliations:
  • Electrical and Computer Engineering, University of California, Santa Barbara;Electrical and Computer Engineering, University of California, Santa Barbara;Electrical and Computer Engineering, University of California, Santa Barbara

  • Venue:
  • DATE '00 Proceedings of the conference on Design, automation and test in Europe
  • Year:
  • 2000

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Abstract